As the largest dollar volume portion of the semiconductor industry, memories appear in every computer, printer, home game console and car; as well as a growing number of home appliances. Total memory sales were $124B in 2017, out of $412B worldwide semiconductor sales. DRAM sales alone grew by 77% in 2017, to a total of $72B.
Since the late 1990s, four increasingly capable Double Data Rate (DDR) Synchronous DRAM architectures have evolved.
The first generation, DDR, doubled the rate of information flow to and from the memory device as compared to single-data-rate synchronous DRAMs. To meet the resulting very tight timing requirements, a new circuit called the delay locked loop was introduced.
The second generation, DDR2, added several features to improve device usability. In particular, on-die termination (ODT) improved signal integrity and reduced external component count.
The third generation, DDR3, provided a refined ODT capability and further defined external device timing in terms of clock cycles instead of internal device parameters.
The fourth generation, DDR4, continued increasing storage capacity and improving the rate of data transmission. But it also emphasized reducing power by many architecture modifications and feature additions.
This course discusses the characteristics and advantages of each of those architectures in a clear and concise manner that any technically trained person can understand. You will be introduced to and become familiar with concepts such as CAS latency, burst length, delay locked loops, on-die termination, prefetch, mode registers and redundancy. Memory packaging in dual in-line memory modules (DIMMs) is also discussed.
This course builds on, but is independent of, Memories in Computers—Part 1. No math beyond high school algebra is required.