With the recognition of the Professional Engineering status for the practice of Computer Engineering in April of 2009, the practice of Control Systems Engineering in October of 2011, and the practice of Software Engineering in April of 2013, there has been the need for specialized continuing education courses related to these practices. Computer Engineering majors may have taken a course with some component of digital design without using Verilog, or may have had a course using the VHDL language. Control Systems engineers will find Verilog to be a useful tool for modeling and simulating real-time hardware and embedded systems for control applications, Software engineers can apply the principles of the concurrent parallel system representations available in Verilog for numerous applications. Other disciplines, including Electrical Engineers will also find the digital design practices encapsulated in Verilog useful all the way to the device level representations available in the language.
We assume that all readers are familiar with digital design concepts, but are interested in an introduction to the capabilities of the Verilog Design Language and how to use it in the design practice. Likewise, we assume that readers generally have rudimentary experience with computer languages, text editors, and general concepts of computer program compilation.
We lead the reader through installation of Free, Open Source Software tools to enter designs, compile and display results, then take the reader through the Behavioral, RTL, and Structural levels of abstraction available, illustrating with simple examples. This course is not exhaustive on the topic but makes a case for the value and usage of Verilog in Digital Design.