This course introduces the Phase-Lock Loop (PLL) with considerations from classical feedback theory producing a simple analog loop for demonstration purposes. The components are analyzed, linearizing them as required and showing the second-order nature of the loop with the PZ compensation filter for stability. The PLL capability as a Frequency-Shift Keyed (FSK) receiver demodulator for a Frequency-Modulated (FM) signal is demonstrated.
The Costas Loop variant of the PLL for double-sideband, suppressed-carrier synchronization using a Bi-Phase modulated signal is introduced, as well as the "Double-Loop" variant of the Costas Loop, showing the equivalence of the saturated signal paths for the Bi-Phase modulation in a summing loop, and the requirements for a difference term for Quadri-Phase Shift Keyed (QPSK) signals. The 180° phase uncertainty associated with the receiver synchronization is shown and discussed.
A digital PLL for frequency synthesis applications is demonstrated with the relationships between loop bandwidth and channel spacing shown. The "Exclusive-OR" logic function is demonstrated as a phase detector and the Phase-Frequency Detector (PFD) and Sink-Source-Float (SSF) implementations are introduced. The stability requirements for the components and the design of a PZ compensator for the digital PLL, including the use of a transconductance and impedance for loop filter application are discussed.
The effects of the sampling delay on the magnitude and phase characteristics of the loop are discussed.
The time and frequency domain performance of a macro-model using the parameters developed show that the discrete-time performance is well predicted, but that there are noise effects from the PU/PD pulses in the PFD.
Fractional-N synthesis technique is introduced and contrasted between the averaging and Δ-Σ modulator approaches to the oversampling used in the Fractional-N approach.
The engineer who completes this course should be able to design a working Phase Lock Loop, making it stable for their application.